A STUDY TO UNDERSTAND NEXT-GENERATION COMPUTER MEMORY ARCHITECTURES THROUGH THE USE OF MODELING AND LEVERAGING EMERGING NON-VOLATILE MEMORIES

Abstract

Energy efficiency in computer system architecture is of the utmost importance nowadays. The common belief is that as CMOS technology becomes smaller, the leakage would increase exponentially since traditional CMOS scaling theory predicts that threshold and supply voltages were decrease in response to device sizes. As a result, methods of the present generation see leaky power as rival to dynamic power. Prior to power budget leakage being an important issue, there has to be a boom of groundbreaking, industry-altering technologies. In the field of non-volatile memory technology, there have been several exciting new advancements. “Resistive Random Access Memory” (ReRAM), “Phase-Change Random Access Memory” (PCRAM), and “Spin-Torque-Transfer Random Access Memory” (MRAM, STTRAM) are all examples of modern non-volatile memories that have appealing properties including low access energy, high cell compactness, and excellent access performance. So, it's great to see these new non-volatile memory technologies being used to build low-power, high-performance computers in the future. Since these novel non-volatile memory technologies are still in their early stages of development, further academic research is required to demonstrate their worth. In light of this, this dissertation investigates three strategies for assisting these novel types of non-volatile memory. Space, power consumption, and circuit-level performance models of several nonvolatile memory types serve as the starting points. Secondly, they propose and evaluate several architecture-level strategies to mitigate write operations' detrimental impacts on non-volatile memory. Lastly, they conduct case studies of real-world applications for this state-of-the-art technology.